module arbiter3
(
	// Multiple Master Port0
	input  [31:0] WBM0_ADR_O,
	input  [31:0] WBM0_DAT_O,
	output [31:0] WBM0_DAT_I,
	input   [3:0] WBM0_SEL_O,
	input         WBM0_WE_O,
	output        WBM0_ACK_I,
	output        WBM0_ERR_I,
	output        WBM0_RTY_I,
	input   [2:0] WBM0_CTI_O,
	input   [1:0] WBM0_BTE_O,
	input         WBM0_LOCK_O,
	input         WBM0_CYC_O,
	input         WBM0_STB_O,

	// Multiple Master Port1
	input  [31:0] WBM1_ADR_O,
	input  [31:0] WBM1_DAT_O,
	output [31:0] WBM1_DAT_I,
	input   [3:0] WBM1_SEL_O,
	input         WBM1_WE_O,
	output        WBM1_ACK_I,
	output        WBM1_ERR_I,
	output        WBM1_RTY_I,
	input   [2:0] WBM1_CTI_O,
	input   [1:0] WBM1_BTE_O,
	input         WBM1_LOCK_O,
	input         WBM1_CYC_O,
	input         WBM1_STB_O,

	// Multiple Master Port2
	input  [31:0] WBM2_ADR_O,
	input  [31:0] WBM2_DAT_O,
	output [31:0] WBM2_DAT_I,
	input   [3:0] WBM2_SEL_O,
	input         WBM2_WE_O,
	output        WBM2_ACK_I,
	output        WBM2_ERR_I,
	output        WBM2_RTY_I,
	input   [2:0] WBM2_CTI_O,
	input   [1:0] WBM2_BTE_O,
	input         WBM2_LOCK_O,
	input         WBM2_CYC_O,
	input         WBM2_STB_O,

	// Single Slave Port
	output [31:0] WBS_ADR_I,
	output [31:0] WBS_DAT_I,
	input  [31:0] WBS_DAT_O,
	output  [3:0] WBS_SEL_I,
	output        WBS_WE_I,
	input         WBS_ACK_O,
	input         WBS_ERR_O,
	input         WBS_RTY_O,
	output  [2:0] WBS_CTI_I,
	output  [1:0] WBS_BTE_I,
	output        WBS_LOCK_I,
	output        WBS_CYC_I,
	output        WBS_STB_I,

	input clk,
	input reset
);

	wire [31:0] WBM0_DAT_I_INT;
	wire [31:0] WBM0_DAT_O_INT;
	wire  [3:0] WBM0_SEL_O_INT;

	wire [31:0] WBM1_DAT_I_INT;
	wire [31:0] WBM1_DAT_O_INT;
	wire  [3:0] WBM1_SEL_O_INT;

	wire [31:0] WBM2_DAT_I_INT;
	wire [31:0] WBM2_DAT_O_INT;
	wire  [3:0] WBM2_SEL_O_INT;

	wire [31:0] WBS_DAT_O_INT;
	wire [31:0] WBS_DAT_I_INT;
	wire  [3:0] WBS_SEL_I_INT;

	assign WBS_DAT_I = WBS_DAT_I_INT;
	assign WBS_SEL_I = WBS_SEL_I_INT;
	assign WBS_DAT_O_INT = WBS_DAT_O;

	assign WBM0_DAT_I = WBM0_DAT_I_INT;
	assign WBM0_SEL_O_INT = WBM0_SEL_O;
	assign WBM0_DAT_O_INT = WBM0_DAT_O;

	assign WBM1_DAT_I = WBM1_DAT_I_INT;
	assign WBM1_SEL_O_INT = WBM1_SEL_O;
	assign WBM1_DAT_O_INT = WBM1_DAT_O;

	assign WBM2_DAT_I = WBM2_DAT_I_INT;
	assign WBM2_SEL_O_INT = WBM2_SEL_O;
	assign WBM2_DAT_O_INT = WBM2_DAT_O;


	reg [2:0] selected; // which master is selected.
	reg locked;

	always @(posedge clk or posedge reset)
	begin
		if (reset) begin
			selected <= #1 0;
			locked   <= #1 0;
		end
		else begin
			if (selected == 0) begin
				if (WBM0_STB_O) begin
					selected <= #1 3'd1;
					locked   <= #1 WBM0_LOCK_O;
				end
				else if (WBM1_STB_O) begin
					selected <= #1 3'd2;
					locked   <= #1 WBM1_LOCK_O;
				end
				else if (WBM2_STB_O) begin
					selected <= #1 3'd3;
					locked   <= #1 WBM2_LOCK_O;
				end
			end
			else if (selected == 3'd1) begin
				if ((WBS_ACK_O || WBS_ERR_O || locked) && ((WBM0_CTI_O == 3'b000) || (WBM0_CTI_O == 3'b111) || locked) && !WBM0_LOCK_O) begin
					selected <= #1 0;
					locked <= #1 0;
				end
			end
			else if (selected == 3'd2) begin
				if ((WBS_ACK_O || WBS_ERR_O || locked) && ((WBM1_CTI_O == 3'b000) || (WBM1_CTI_O == 3'b111) || locked) && !WBM1_LOCK_O) begin
					selected <= #1 0;
					locked <= #1 0;
				end
			end
			else if (selected == 3'd3) begin
				if ((WBS_ACK_O || WBS_ERR_O || locked) && ((WBM2_CTI_O == 3'b000) || (WBM2_CTI_O == 3'b111) || locked) && !WBM2_LOCK_O) begin
					selected <= #1 0;
					locked <= #1 0;
				end
			end
		end
	end


	assign WBS_ADR_I = 
		(selected == 3'd1 ? WBM0_ADR_O : 
		(selected == 3'd2 ? WBM1_ADR_O : 
		(selected == 3'd3 ? WBM2_ADR_O : 
		0)));
	assign WBS_DAT_I_INT = 
		(selected == 3'd1 ? WBM0_DAT_O_INT : 
		(selected == 3'd2 ? WBM1_DAT_O_INT : 
		(selected == 3'd3 ? WBM2_DAT_O_INT : 
		0)));
	assign WBS_SEL_I_INT = 
		(selected == 3'd1 ? WBM0_SEL_O_INT : 
		(selected == 3'd2 ? WBM1_SEL_O_INT : 
		(selected == 3'd3 ? WBM2_SEL_O_INT : 
		0)));
	assign WBS_WE_I = 
		(selected == 3'd1 ? WBM0_WE_O : 
		(selected == 3'd2 ? WBM1_WE_O : 
		(selected == 3'd3 ? WBM2_WE_O : 
		0)));
	assign WBS_CTI_I = 
		(selected == 3'd1 ? WBM0_CTI_O : 
		(selected == 3'd2 ? WBM1_CTI_O : 
		(selected == 3'd3 ? WBM2_CTI_O : 
		0)));
	assign WBS_BTE_I = 
		(selected == 3'd1 ? WBM0_BTE_O : 
		(selected == 3'd2 ? WBM1_BTE_O : 
		(selected == 3'd3 ? WBM2_BTE_O : 
		0)));
	assign WBS_LOCK_I = 
		(selected == 3'd1 ? WBM0_LOCK_O : 
		(selected == 3'd2 ? WBM1_LOCK_O : 
		(selected == 3'd3 ? WBM2_LOCK_O : 
		0)));
	assign WBS_CYC_I = 
		(selected == 3'd1 ? WBM0_CYC_O : 
		(selected == 3'd2 ? WBM1_CYC_O : 
		(selected == 3'd3 ? WBM2_CYC_O : 
		0)));
	assign WBS_STB_I = 
		(selected == 3'd1 ? WBM0_STB_O : 
		(selected == 3'd2 ? WBM1_STB_O : 
		(selected == 3'd3 ? WBM2_STB_O : 
		0)));

	assign WBM0_DAT_I_INT = WBS_DAT_O_INT;
	assign WBM0_ACK_I = (selected == 3'd1 ? WBS_ACK_O : 0);
	assign WBM0_ERR_I = (selected == 3'd1 ? WBS_ERR_O : 0);
	assign WBM0_RTY_I = (selected == 3'd1 ? WBS_RTY_O : 0);

	assign WBM1_DAT_I_INT = WBS_DAT_O_INT;
	assign WBM1_ACK_I = (selected == 3'd2 ? WBS_ACK_O : 0);
	assign WBM1_ERR_I = (selected == 3'd2 ? WBS_ERR_O : 0);
	assign WBM1_RTY_I = (selected == 3'd2 ? WBS_RTY_O : 0);

	assign WBM2_DAT_I_INT = WBS_DAT_O_INT;
	assign WBM2_ACK_I = (selected == 3'd3 ? WBS_ACK_O : 0);
	assign WBM2_ERR_I = (selected == 3'd3 ? WBS_ERR_O : 0);
	assign WBM2_RTY_I = (selected == 3'd3 ? WBS_RTY_O : 0);

endmodule























`include "../components/spi_flash/rtl/verilog/spi_flash.v"
`include "../components/spi_flash/rtl/verilog/wb_intf.v"
`include "../components/spi_flash/rtl/verilog/spi_flash_intf.v"
`include "../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v"




module lm32 ( 
	input  clk_i,
	input  reset_n,
	output SPIFlashCEJ,
	output SPIFlashSCK,
	output SPIFlashSI,
	input  SPIFlashSO,
	output SPIFlashWPJ,
	inout [`SDR_DATA_WIDTH-1:0] sdramsdr_DQ,
	output [12-1:0] sdramsdr_A,
	output [2-1:0] sdramsdr_BA,
	output sdramsdr_CKE,
	output sdramsdr_CSn,
	output sdramsdr_RASn,
	output sdramsdr_CASn,
	output sdramsdr_WEn,
	output [`SDR_DATA_WIDTH/8-1:0]  sdramsdr_DQM,
	output sdramsdr_CLK,
	input uartSIN,
	output uartSOUT
);
genvar i;

wire [31:0] SPIFlashS_DAT_O;
wire   SPIFlashS_ACK_O;
wire   SPIFlashS_ERR_O;
wire   SPIFlashS_RTY_O;
wire SPIFlashS_en;

wire [31:0] sdramS_DAT_O;
wire   sdramS_ACK_O;
wire   sdramS_ERR_O;
wire   sdramS_RTY_O;
wire sdramS_en;


















wire [31:0] SPIFlashS_DAT_I;
assign SPIFlashS_DAT_I = SHAREDBUS_DAT_I[31:0];
wire [3:0] SPIFlashS_SEL_I;
assign SPIFlashS_SEL_I = SHAREDBUS_SEL_I;
assign SPIFlashS_en = (SHAREDBUS_ADR_I[31:24] == 8'b00000001);
spi_flash 
#(
.LATTICE_FAMILY("MachXO2"),
.S_WB_DAT_WIDTH(32),
.S_WB_ADR_WIDTH(32),
.C_PORT_ENABLE(0),
.C_WB_DAT_WIDTH(32),
.C_WB_ADR_WIDTH(11),
.CLOCK_SEL(32'h0),
.PAGE_PRG_BUF_ENA(0),
.PAGE_READ_BUF_ENA(0),
.SPI_READ(32'h3),
.SPI_FAST_READ(32'hb),
.SPI_BYTE_PRG(32'h2),
.SPI_PAGE_PRG(32'h2),
.SPI_BLK1_ERS(32'hd8),
.SPI_BLK2_ERS(32'hd8),
.SPI_BLK3_ERS(32'hd8),
.SPI_CHIP_ERS(32'hc7),
.SPI_WRT_ENB(32'h6),
.SPI_WRT_DISB(32'h4),
.SPI_READ_STAT(32'h5),
.SPI_WRT_STAT(32'h1),
.SPI_PWD_DOWN(32'hb9),
.SPI_PWD_UP(32'hab),
.SPI_DEV_ID(32'h9f))
 SPIFlash( 
.S_ADR_I(SHAREDBUS_ADR_I[31:0]),
.S_DAT_I(SPIFlashS_DAT_I[31:0]),
.S_DAT_O(SPIFlashS_DAT_O[31:0]),
.S_SEL_I(SPIFlashS_SEL_I[3:0]),
.S_WE_I(SHAREDBUS_WE_I),
.S_ACK_O(SPIFlashS_ACK_O),
.S_ERR_O(SPIFlashS_ERR_O),
.S_RTY_O(SPIFlashS_RTY_O),
.S_CTI_I(SHAREDBUS_CTI_I),
.S_BTE_I(SHAREDBUS_BTE_I),
.S_LOCK_I(SHAREDBUS_LOCK_I),
.S_CYC_I(SHAREDBUS_CYC_I & SPIFlashS_en),
.S_STB_I(SHAREDBUS_STB_I & SPIFlashS_en),
.CEJ(SPIFlashCEJ),
.SCK(SPIFlashSCK),
.SI(SPIFlashSI),
.SO(SPIFlashSO),
.WPJ(SPIFlashWPJ),
.CLK_I(clk_i), .RST_I(sys_reset));





wire [31:0] sdramS_DAT_I;
assign sdramS_DAT_I = SHAREDBUS_DAT_I[31:0];
wire [3:0] sdramS_SEL_I;
assign sdramS_SEL_I = SHAREDBUS_SEL_I;
assign sdramS_en = (SHAREDBUS_ADR_I[31:25] == 7'b0000001);
wb_sdr_ctrl 
#(
.LATTICE_FAMILY("MachXO2"),
.LATTICE_DEVICE("LCMXO2-7000HC"),
.SYS_FREQ("24"),
.SDRAM_FREQ("48"))
 sdram( 
.S_ADR_I(SHAREDBUS_ADR_I[31:0]),
.S_DAT_I(sdramS_DAT_I[31:0]),
.S_DAT_O(sdramS_DAT_O[31:0]),
.S_SEL_I(sdramS_SEL_I[3:0]),
.S_WE_I(SHAREDBUS_WE_I),
.S_ACK_O(sdramS_ACK_O),
.S_ERR_O(sdramS_ERR_O),
.S_RTY_O(sdramS_RTY_O),
.S_CTI_I(SHAREDBUS_CTI_I),
.S_BTE_I(SHAREDBUS_BTE_I),
.S_LOCK_I(SHAREDBUS_LOCK_I),
.S_CYC_I(SHAREDBUS_CYC_I & sdramS_en),
.S_STB_I(SHAREDBUS_STB_I & sdramS_en),
.sdr_DQ(sdramsdr_DQ),
.sdr_A(sdramsdr_A),
.sdr_BA(sdramsdr_BA),
.sdr_CKE(sdramsdr_CKE),
.sdr_CSn(sdramsdr_CSn),
.sdr_RASn(sdramsdr_RASn),
.sdr_CASn(sdramsdr_CASn),
.sdr_WEn(sdramsdr_WEn),
.sdr_DQM(sdramsdr_DQM),
.sdr_CLK(sdramsdr_CLK),
.CLK_I (clk_i), .RST_I (sys_reset));


wire [7:0] uartUART_DAT_I;
assign uartUART_DAT_I = ((
	SHAREDBUS_ADR_I[1:0] == 2'b00) ? SHAREDBUS_DAT_I[31:24] : ((
	SHAREDBUS_ADR_I[1:0] == 2'b01) ? SHAREDBUS_DAT_I[23:16] : ((
	SHAREDBUS_ADR_I[1:0] == 2'b10) ? SHAREDBUS_DAT_I[15:8] : SHAREDBUS_DAT_I[7:0])));
wire uartUART_SEL_I;
assign uartUART_SEL_I = ((
	SHAREDBUS_ADR_I[1:0] == 2'b00) ? SHAREDBUS_SEL_I[3] : ((
	SHAREDBUS_ADR_I[1:0] == 2'b01) ? SHAREDBUS_SEL_I[2] : ((
	SHAREDBUS_ADR_I[1:0] == 2'b10) ? SHAREDBUS_SEL_I[1] : SHAREDBUS_SEL_I[0])));
assign uartUART_en = (SHAREDBUS_ADR_I[31:4] == 28'b1000000000000000000000000000);



wire [31:0] bootromEBR_DAT_I;
assign bootromEBR_DAT_I = SHAREDBUS_DAT_I[31:0];
wire [3:0] bootromEBR_SEL_I;
assign bootromEBR_SEL_I = SHAREDBUS_SEL_I;
assign bootromEBR_en = (SHAREDBUS_ADR_I[31:12] == 20'b00000000000000000000);
wb_ebr_ctrl 
#(
.SIZE(4096),
.EBR_WB_DAT_WIDTH(32),
.INIT_FILE_NAME("none"),
.INIT_FILE_FORMAT("hex"))
 bootrom( 
.EBR_ADR_I(SHAREDBUS_ADR_I[31:0]),
.EBR_DAT_I(bootromEBR_DAT_I[31:0]),
.EBR_DAT_O(bootromEBR_DAT_O[31:0]),
.EBR_SEL_I(bootromEBR_SEL_I[3:0]),
.EBR_WE_I(SHAREDBUS_WE_I),
.EBR_ACK_O(bootromEBR_ACK_O),
.EBR_ERR_O(bootromEBR_ERR_O),
.EBR_RTY_O(bootromEBR_RTY_O),
.EBR_CTI_I(SHAREDBUS_CTI_I),
.EBR_BTE_I(SHAREDBUS_BTE_I),
.EBR_LOCK_I(SHAREDBUS_LOCK_I),
.EBR_CYC_I(SHAREDBUS_CYC_I & bootromEBR_en),
.EBR_STB_I(SHAREDBUS_STB_I & bootromEBR_en),
.CLK_I (clk_i), .RST_I (sys_reset));


wire [31:0] scratchpadEBR_DAT_I;
assign scratchpadEBR_DAT_I = SHAREDBUS_DAT_I[31:0];
wire [3:0] scratchpadEBR_SEL_I;
assign scratchpadEBR_SEL_I = SHAREDBUS_SEL_I;
assign scratchpadEBR_en = (SHAREDBUS_ADR_I[31:12] == 20'b00000000000000000001);
wb_ebr_ctrl 
#(
.SIZE(4096),
.EBR_WB_DAT_WIDTH(32),
.INIT_FILE_NAME("none"),
.INIT_FILE_FORMAT("hex"))
 scratchpad( 
.EBR_ADR_I(SHAREDBUS_ADR_I[31:0]),
.EBR_DAT_I(scratchpadEBR_DAT_I[31:0]),
.EBR_DAT_O(scratchpadEBR_DAT_O[31:0]),
.EBR_SEL_I(scratchpadEBR_SEL_I[3:0]),
.EBR_WE_I(SHAREDBUS_WE_I),
.EBR_ACK_O(scratchpadEBR_ACK_O),
.EBR_ERR_O(scratchpadEBR_ERR_O),
.EBR_RTY_O(scratchpadEBR_RTY_O),
.EBR_CTI_I(SHAREDBUS_CTI_I),
.EBR_BTE_I(SHAREDBUS_BTE_I),
.EBR_LOCK_I(SHAREDBUS_LOCK_I),
.EBR_CYC_I(SHAREDBUS_CYC_I & scratchpadEBR_en),
.EBR_STB_I(SHAREDBUS_STB_I & scratchpadEBR_en),
.CLK_I (clk_i), .RST_I (sys_reset));


endmodule