// ================================================================== // >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< // ------------------------------------------------------------------ // Copyright (c) 2006-2011 by Lattice Semiconductor Corporation // ALL RIGHTS RESERVED // ------------------------------------------------------------------ // // IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM. // // Permission: // // Lattice Semiconductor grants permission to use this code // pursuant to the terms of the Lattice Semiconductor Corporation // Open Source License Agreement. // // Disclaimer: // // Lattice Semiconductor provides no warranty regarding the use or // functionality of this code. It is the user's responsibility to // verify the user’s design for consistency and functionality through // the use of formal verification methods. // // -------------------------------------------------------------------- // // Lattice Semiconductor Corporation // 5555 NE Moore Court // Hillsboro, OR 97214 // U.S.A // // TEL: 1-800-Lattice (USA and Canada) // 503-286-8001 (other locations) // // web: http://www.latticesemi.com/ // email: techsupport@latticesemi.com // // -------------------------------------------------------------------- // FILE DETAILS // Project : LatticeMico32 // File : lm32_logic_op.v // Title : Logic operations (and / or / not etc) // Dependencies : lm32_include.v // Version : 6.1.17 // : Initial Release // Version : 7.0SP2, 3.0 // : No Change // Version : 3.1 // : No Change // ============================================================================= `include "lm32_include.v" ///////////////////////////////////////////////////// // Module interface ///////////////////////////////////////////////////// module lm32_logic_op ( // ----- Inputs ------- logic_op_x, operand_0_x, operand_1_x, // ----- Outputs ------- logic_result_x ); ///////////////////////////////////////////////////// // Inputs ///////////////////////////////////////////////////// input [`LM32_LOGIC_OP_RNG] logic_op_x; input [`LM32_WORD_RNG] operand_0_x; input [`LM32_WORD_RNG] operand_1_x; ///////////////////////////////////////////////////// // Outputs ///////////////////////////////////////////////////// output [`LM32_WORD_RNG] logic_result_x; reg [`LM32_WORD_RNG] logic_result_x; ///////////////////////////////////////////////////// // Internal nets and registers ///////////////////////////////////////////////////// integer logic_idx; ///////////////////////////////////////////////////// // Combinational Logic ///////////////////////////////////////////////////// always @(*) begin for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1) logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}]; end endmodule