SCUBA, Version Diamond (64-bit) 3.7.1.502
Mon Mar 27 22:47:45 2017

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Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.7_x64\ispfpga\bin\nt64\scuba.exe -w -n serialfifo1k -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 1024 -width 8 -rwidth 8 -no_enable -pe 10 -pf 508 
    Circuit name     : serialfifo1k
    Module type      : ebfifo
    Module Version   : 5.8
    Ports            : 
	Inputs       : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
	Outputs      : Q[7:0], Empty, Full, AlmostEmpty, AlmostFull
    I/O buffer       : not inserted
    EDIF output      : serialfifo1k.edn
    Verilog output   : serialfifo1k.v
    Verilog template : serialfifo1k_tmpl.v
    Verilog testbench: tb_serialfifo1k_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : serialfifo1k.srp
    Element Usage    :
        FIFO8KB : 1
    Estimated Resource Usage:
            EBR : 1