[Device]
Family=machxo2
PartType=LCMXO2-2000HC
PartName=LCMXO2-2000HC-4TG100C
SpeedGrade=4
Package=TQFP100
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=FIFO_DC
CoreRevision=5.8
ModuleName=datafifo
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=03/26/2017
Time=21:09:28

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
FIFOImp=EBR Only
RDepth=1024
RWidth=16
WDepth=1024
WWidth=16
regout=0
CtrlByRdEn=0
ClockEn=0
EmpFlg=1
PeMode=Static - Single Threshold
PeAssert=256
PeDeassert=12
FullFlg=1
PfMode=Static - Single Threshold
PfAssert=768
PfDeassert=506
Reset=Async
Reset1=Sync
RDataCount=0
WDataCount=0
EnECC=0

[Command]
cmd_line= -w -n datafifo -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 1024 -width 16 -rwidth 16 -no_enable -pe 256 -pf 768