/*
     Address 0 : data LSB - activate on read
             1 : data
             2 : data
             3 : data MSB - activate on write
             4 : address LSB
             5 : address 
             6 : address
             7 : address MSB
*/

module wb_proxy (

	// Sychronous pass-thru
	input         clk_i,
	input         rst_i,

	// Wishbone slave interface
	input   [2:0] slave_adr_i,
	output  [7:0] slave_dat_o,
	input   [7:0] slave_dat_i,
	input         slave_we_i,
	input         slave_stb_i,
	input         slave_cyc_i,
	output        slave_ack_o,

	// Wishbone master interface
	output [31:0] master_adr_o,
	input  [31:0] master_dat_i,
	output [31:0] master_dat_o,
	output  [3:0] master_sel_o,
	output        master_we_o,
	output        master_stb_o,
	output        master_cyc_o,
	input         master_ack_i
);

	reg [31:0] latch_addr;
	reg [24:0] latch_data;

	wire activate;

	assign active = ( slave_we_i & (slave_adr_i == 3))
	              | (!slave_we_i & (slave_adr_i == 0));

	assign slave_ack_o = active ? master_ack_i : slave_stb_i;

	assign slave_dat_o =
		 (slave_adr_i == 0) ? master_dat_i[7:0] :
		 (slave_adr_i == 1) ? latch_data[7:0]   :
		 (slave_adr_i == 2) ? latch_data[15:8]  :
		 (slave_adr_i == 3) ? latch_data[23:16] :
		 (slave_adr_i == 4) ? latch_addr[7:0]   :
		 (slave_adr_i == 5) ? latch_addr[15:8]  :
		 (slave_adr_i == 6) ? latch_addr[23:16] : latch_addr[31:24];

	always @(posedge clk_i or posedge rst_i)
	begin
		if (rst_i)
		begin
			latch_addr <= 32'h00000000;
			latch_data <= 24'h000000;
		end
		else if (slave_stb_i)
		begin

			if (slave_we_i)
			begin
				case (slave_adr_i)
				0 : begin
					latch_data[7:0]   <= slave_dat_i;
				end
				1 : begin
					latch_data[15:8]  <= slave_dat_i;
				end
				2 : begin
					latch_data[23:16] <= slave_dat_i;
				end
				4 : begin
					latch_addr[7:0]   <= slave_dat_i;
				end
				5 : begin
					latch_addr[15:8]  <= slave_dat_i;
				end
				6 : begin
					latch_addr[23:16] <= slave_dat_i;
				end
				7 : begin
					latch_addr[31:24] <= slave_dat_i;
				end
				endcase
			end
			else
			begin
				if (slave_adr_i == 0)
					latch_data <= master_dat_i[31:8];
			end	
		end
	end

	assign master_adr_o = (active & slave_stb_i) ? latch_addr  : 0;
	assign master_dat_o = (active & slave_stb_i) ? { slave_dat_i, latch_data } : 0;
	assign master_sel_o = (active & slave_stb_i) ? 4'b1111     : 0;
	assign master_we_o  = (active & slave_stb_i) ? slave_we_i  : 0;
	assign master_stb_o =  active & slave_stb_i;
	assign master_cyc_o = (active & slave_stb_i) ? slave_cyc_i : 0;

endmodule