/*

   Copyright (c) 2006-2011 by Lattice Semiconductor Corporation

	Name:   lm8_io_cntl.v

	Description:  I/O controller


   Permission:

	Lattice Semiconductor grants permission to use this code for use
	in synthesis for any Lattice programmable logic product.  Other
	use of this code, including the selling or duplication of any
	portion is strictly prohibited.

   Disclaimer:

	This VHDL or Verilog source code is intended as a design reference
	which illustrates how these types of functions can be implemented.
	It is the user's responsibility to verify their design for
	consistency and functionality through the use of formal
	verification methods.  Lattice Semiconductor provides no warranty
	regarding the use or functionality of this code.

	 Lattice Semiconductor Corporation
	 5555 NE Moore Court
	 Hillsboro, OR 97124
	 U.S.A

	 TEL: 1-800-Lattice (USA and Canada)
	 408-826-6000 (other locations)

	 web: http://www.latticesemi.com/
	 email: techsupport@latticesemi.com
*/

module lm8_io_cntl (

	input clk,
	input rst_n,
	input import_,
	input importi,
	input export_,
	input exporti,
	input ssp,
	input sspi,
	input lsp,
	input lspi,
	input addr_cyc,
	input ext_addr_cyc,
	input [4:0] addr_rb,
	input [7:0] dout_rd,
	input [7:0] dout_rb,
	output reg [7:0] ext_addr,
	output reg [7:0] ext_dout,
	output reg ext_mem_wr,
	output reg ext_mem_rd,
	output reg ext_io_wr,
	output reg ext_io_rd
);

	reg [7:0] ext_addr_nxt;
	reg [7:0] ext_dout_nxt;
	reg       ext_mem_wr_nxt;
	reg       ext_mem_rd_nxt;
	reg       ext_io_wr_nxt;
	reg       ext_io_rd_nxt;

	always @(/*AUTOSENSE*/addr_cyc or addr_rb or dout_rb or dout_rd
	  or exporti or ext_addr_cyc or importi or lsp or lspi
	  or ssp or sspi or import_ or export_)
	begin
		if ((export_ || exporti) && (addr_cyc || ext_addr_cyc))
			ext_io_wr_nxt = 1'b1;
		else
			ext_io_wr_nxt = 1'b0;

		if ((import_ || importi) && (addr_cyc || ext_addr_cyc))
			ext_io_rd_nxt = 1'b1;
		else
			ext_io_rd_nxt = 1'b0;

		if ((ssp || sspi) && (addr_cyc || ext_addr_cyc))
			ext_mem_wr_nxt = 1'b1;
		else
			ext_mem_wr_nxt = 1'b0;

		if ((lsp || lspi) && (addr_cyc || ext_addr_cyc))
			ext_mem_rd_nxt = 1'b1;
		else
			ext_mem_rd_nxt = 1'b0;

		if (export_ || import_ || lsp || ssp)
			ext_addr_nxt = {3'b000, addr_rb};
		else
			ext_addr_nxt = dout_rb;

		ext_dout_nxt = dout_rd;
	end

	always @(posedge clk or negedge rst_n)
	begin
		if (!rst_n)
		begin
			ext_addr   <= #1 0;
			ext_dout   <= #1 0;
			ext_io_wr  <= #1 0;
			ext_io_rd  <= #1 0;
			ext_mem_wr <= #1 0;
			ext_mem_rd <= #1 0;
		end
		else
		begin
			ext_addr   <= #1 ext_addr_nxt;
			ext_dout   <= #1 ext_dout_nxt;
			ext_io_wr  <= #1 ext_io_wr_nxt;
			ext_io_rd  <= #1 ext_io_rd_nxt;
			ext_mem_wr <= #1 ext_mem_wr_nxt;
			ext_mem_rd <= #1 ext_mem_rd_nxt;
		end
	end

endmodule