/*

Enable pulls on 16-bit signals to keep them at a sane constant state










I/O block at configurable base address
  - EFB address
  - EFB data
  - SPI CS
  - SPI data
  - 








*/



module isa_wb_master
(
	// Run-time config

	input             cfg_WIDE,     // 16-bit mode
	input [9:3]             cfg_IOBASE,







	// ISA pads

	inout      [15:0] isa_D,        // Data bus (x16)
	input      [19:0] isa_SA,       // System address bus (x20)
	input     [23:17] isa_UA,       // Unlatched address bus (x7)
	input             isa_ALE,      // Address latch enable
	output            isa_IOCHRDY,  // I/O channel ready
	input             isa_SMEMW,    // System memory write strobe
	input             isa_SMEMR,    // System memory read strobe
	input             isa_MEMW,     // memory write strobe
	input             isa_MEMR,     // memory read strobe
	input             isa_IOW,      // I/O write strobe
	input             isa_IOR,      // I/O read strobe
	input             isa_SBHE,     // System bus high enable
	output            isa_MEM16n,   // 16-bit memory select
	output            isa_IO16n,    // 16-bit I/O select
	output reg        isa_ZWSn,     // Zero wait state
	input             isa_AEN,      // DMA address enable

	input             isa_CS,       // Overall card select
 
	input             wb_clk_i,     // Synchronous bus clock
	input             wb_rst_i,     // Asynchronous bus reset

	input      [15:0] wb_dat_i,     // Input data
	output reg [15:0] wb_dat_o,     // Output data
	output reg [23:0] wb_adr_o,     // Address
	output reg        wb_WE,        // Cycle direction
	output reg        wb_tga_o,     // Address tag: 1 = I/O, 0 = MEM
	output reg [ 1:0] wb_sel_o,     // Byte path selection
	output            wb_CE,        // Bus cycle enable
	input             wb_ack_i      // Slave completion ack
);

	// Strobe aggregation - positive logic

	wire    io_cycle =  (isa_IOW | isa_IOR) & !isa_AEN;
	wire   mem_cycle = isa_SMEMW | isa_MEMW | isa_SMEMR | isa_MEMR;
	wire write_cycle = isa_SMEMW | isa_MEMW | isa_IOW;


	// Address propagation

	reg [23:17] isa_LA;
	wire [23:0] isa_A;

	always @(negedge isa_ALE)
		isa_LA <= isa_UA;

	assign isa_A[23:20] = isa_LA[23:20];
	assign isa_A [19:0] = isa_SA[19:0];










	wire cfg_XMS[31:0] = { 32'b0011_1111_1111_1111_0000_0000_0000_0000 };

	// Only assert zero wait for XMS based on backfill (pure combinatorial)

	wire [4:0] zero_IDX = { isa_LA[23:19] };

	assign isa_ZWSn = ~cfg_XMS[ zero_IDX ];
/*
	always @(*)
	begin
		case (zero_IDX)
		5'd0  : isa_ZWSn = ~cfg_XMS[0];
		5'd1  : isa_ZWSn = ~cfg_XMS[1];
		5'd2  : isa_ZWSn = ~cfg_XMS[2];
		5'd3  : isa_ZWSn = ~cfg_XMS[3];
		5'd4  : isa_ZWSn = ~cfg_XMS[4];
		5'd5  : isa_ZWSn = ~cfg_XMS[5];
		5'd6  : isa_ZWSn = ~cfg_XMS[6];
		5'd7  : isa_ZWSn = ~cfg_XMS[7];
		5'd8  : isa_ZWSn = ~cfg_XMS[8];
		5'd9  : isa_ZWSn = ~cfg_XMS[9];
		5'd10 : isa_ZWSn = ~cfg_XMS[10];
		5'd11 : isa_ZWSn = ~cfg_XMS[11];
		5'd12 : isa_ZWSn = ~cfg_XMS[12];
		5'd13 : isa_ZWSn = ~cfg_XMS[13];
		5'd14 : isa_ZWSn = ~cfg_XMS[14];
		5'd15 : isa_ZWSn = ~cfg_XMS[15];
		5'd16 : isa_ZWSn = ~cfg_XMS[16];
		5'd17 : isa_ZWSn = ~cfg_XMS[17];
		5'd18 : isa_ZWSn = ~cfg_XMS[18];
		5'd19 : isa_ZWSn = ~cfg_XMS[19];
		5'd20 : isa_ZWSn = ~cfg_XMS[20];
		5'd21 : isa_ZWSn = ~cfg_XMS[21];
		5'd22 : isa_ZWSn = ~cfg_XMS[22];
		5'd23 : isa_ZWSn = ~cfg_XMS[23];
		5'd24 : isa_ZWSn = ~cfg_XMS[24];
		5'd25 : isa_ZWSn = ~cfg_XMS[25];
		5'd26 : isa_ZWSn = ~cfg_XMS[26];
		5'd27 : isa_ZWSn = ~cfg_XMS[27];
		5'd28 : isa_ZWSn = ~cfg_XMS[28];
		5'd29 : isa_ZWSn = ~cfg_XMS[29];
		5'd30 : isa_ZWSn = ~cfg_XMS[30];
		5'd31 : isa_ZWSn = ~cfg_XMS[31];
		endcase
	end
*/














	always @(posedge sys_CLK or posedge sys_RST)
	begin
		if (sys_RST) begin
			wb_adr_o <= 0;
			wb_dat_o <= 0;
			wb_cyc_o <= 0;
			wb_stb_o <= 0;
			wb_we_o  <= 0;
			wb_tga_o <= 0;
		end
		else
		begin


			wb_adr_o[19:0]  <= isa_SA;
			wb_adr_o[31:20] <= 0;

			wb_dat_o <= isa_D;

			wb_CE <= io_cycle | mem_cycle;
			wb_WE <= write_cycle;
			wb_tga_o <= io_cycle;



		end
	end










	assign wb_CE = io_cycle || mem_cycle;
	assign wb_WE = write_cycle;


	always @(posedge wb_clk_i)
	  wb_sel_o <= 2'b11;


/*
	input             isa_SBHE,     // System bus high enable

	output reg [ 1:0] wb_sel_o,     // Byte path selection

	input             isa_WIDE,     // 16-bit mode
*/







	assign wb_tga_o = io_cycle;

	/*
	 * ISA -> WB data propagation
	 *
	 */

	assign isa_D = (!wb_we_o && wb_ack_i) ? wb_dat_i : 16'hzzzz;

	always @(posedge wb_clk_i)
		wb_dat_o <= isa_D;


	/*
	 * ISA feedback logic
	 *
	 * Temporarily disabled
	 */

	//assign isa_MEM16n  = ~(isa_CS & mem_cycle);//1'bz;
	//assign isa_IO16n   = ~(isa_CS & io_cycle);//1'bz;
	assign isa_MEM16n  = 1'bz;
	assign isa_IO16n   = 1'bz;
	assign isa_IOCHRDY = 1'bz;

endmodule