SCUBA, Version Diamond_3.1_Production (93)
Tue May 13 15:25:51 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.1\ispfpga\bin\nt\scuba.exe -w -n plla -lang verilog -synth synplify -arch xo2c00 -type pll -fin 20 -fclkop 80 -fclkop_tol 0.0 -fclkos 40 -fclkos_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 0 -trims_r -phase_cntl STATIC -fb_mode 1 -lock 
    Circuit name     : plla
    Module type      : pll
    Module Version   : 5.5
    Ports            : 
	Inputs       : CLKI
	Outputs      : CLKOP, CLKOS, LOCK
    I/O buffer       : not inserted
    EDIF output      : plla.edn
    Verilog output   : plla.v
    Verilog template : plla_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : plla.srp
    Element Usage    :
        EHXPLLJ : 1
    Estimated Resource Usage: