SCUBA, Version Diamond_3.1_Production (93)
Tue May 13 16:28:12 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.1\ispfpga\bin\nt\scuba.exe -w -n pagetable -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdps -device LCMXO2-7000HC -raddr_width 8 -rwidth 16 -waddr_width 8 -wwidth 16 -rnum_words 256 -wnum_words 256 -byte 8 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0 
    Circuit name     : pagetable
    Module type      : RAM_DP
    Module Version   : 6.3
    Ports            : 
	Inputs       : WrAddress[7:0], RdAddress[7:0], Data[15:0], ByteEn[1:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
	Outputs      : Q[15:0]
    I/O buffer       : not inserted
    Memory file      : INIT_ALL_0s
    EDIF output      : pagetable.edn
    Verilog output   : pagetable.v
    Verilog template : pagetable_tmpl.v
    Verilog testbench: tb_pagetable_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : pagetable.srp
    Element Usage    :
        PDPW8KC : 1
    Estimated Resource Usage:
            EBR : 1