[Device]
Family=machxo2
PartType=LCMXO2-7000HC
PartName=LCMXO2-7000HC-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP
CoreRevision=6.2
ModuleName=pagetable
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=05/13/2014
Time=16:28:10

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=256
RData=16
WAddress=256
WData=16
enByte=1
ByteSize=8
OutputEn=1
ClockEn=0
Optimization=Speed
Reset=Sync
Reset1=Sync
Init=0
MemFile=
MemFormat=bin
EnECC=0
Pipeline=0
init_data=0

[FilesGenerated]
=mem

[Command]
cmd_line= -w -n pagetable -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ramdps -device LCMXO2-7000HC -raddr_width 8 -rwidth 16 -waddr_width 8 -wwidth 16 -rnum_words 256 -wnum_words 256 -byte 8 -outdata REGISTERED -cascade -1 -resetmode SYNC -sync_reset -mem_init0