/* Verilog netlist generated by SCUBA Diamond_3.1_Production (93) */
/* Module Version: 5.6 */
/* C:\lscc\diamond\3.1_x64\ispfpga\bin\nt64\scuba.exe -w -n fifo_cmd -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 256 -width 32 -rwidth 8 -regout -resetmode ASYNC -reset_rel SYNC -no_enable -pe 4 -pf 252  */
/* Sun May 18 16:43:06 2014 */


`timescale 1 ns / 1 ps
module fifo_cmd (Data, WrClock, RdClock, WrEn, RdEn, Reset, RPReset, Q, 
    Empty, Full, AlmostEmpty, AlmostFull)/* synthesis NGD_DRC_MASK=1 */;
    input wire [31:0] Data;
    input wire WrClock;
    input wire RdClock;
    input wire WrEn;
    input wire RdEn;
    input wire Reset;
    input wire RPReset;
    output wire [7:0] Q;
    output wire Empty;
    output wire Full;
    output wire AlmostEmpty;
    output wire AlmostFull;

    wire Empty_int;
    wire Full_int;
    wire scuba_vhi;
    wire scuba_vlo;

    defparam fifo_cmd_0_1.FULLPOINTER1 = "0b00111111110000" ;
    defparam fifo_cmd_0_1.FULLPOINTER = "0b01000000000000" ;
    defparam fifo_cmd_0_1.AFPOINTER1 = "0b00111110110000" ;
    defparam fifo_cmd_0_1.AFPOINTER = "0b00111111000000" ;
    defparam fifo_cmd_0_1.AEPOINTER1 = "0b00000000010100" ;
    defparam fifo_cmd_0_1.AEPOINTER = "0b00000000010000" ;
    defparam fifo_cmd_0_1.ASYNC_RESET_RELEASE = "SYNC" ;
    defparam fifo_cmd_0_1.GSR = "DISABLED" ;
    defparam fifo_cmd_0_1.RESETMODE = "ASYNC" ;
    defparam fifo_cmd_0_1.REGMODE = "OUTREG" ;
    defparam fifo_cmd_0_1.CSDECODE_R = "0b11" ;
    defparam fifo_cmd_0_1.CSDECODE_W = "0b11" ;
    defparam fifo_cmd_0_1.DATA_WIDTH_R = 4 ;
    defparam fifo_cmd_0_1.DATA_WIDTH_W = 18 ;
    FIFO8KB fifo_cmd_0_1 (.DI0(Data[0]), .DI1(Data[1]), .DI2(Data[2]), .DI3(Data[3]), 
        .DI4(Data[8]), .DI5(Data[9]), .DI6(Data[10]), .DI7(Data[11]), .DI8(scuba_vlo), 
        .DI9(Data[16]), .DI10(Data[17]), .DI11(Data[18]), .DI12(Data[19]), 
        .DI13(Data[24]), .DI14(Data[25]), .DI15(Data[26]), .DI16(Data[27]), 
        .DI17(scuba_vlo), .CSW0(scuba_vhi), .CSW1(scuba_vhi), .CSR0(RdEn), 
        .CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), .WE(WrEn), 
        .RE(scuba_vhi), .ORE(scuba_vhi), .CLKW(WrClock), .CLKR(RdClock), 
        .RST(Reset), .RPRST(RPReset), .DO0(Q[0]), .DO1(Q[1]), .DO2(Q[2]), 
        .DO3(Q[3]), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), .DO9(), .DO10(), 
        .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), .DO17(), .EF(Empty_int), 
        .AEF(AlmostEmpty), .AFF(AlmostFull), .FF(Full_int));

    VHI scuba_vhi_inst (.Z(scuba_vhi));

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    defparam fifo_cmd_1_0.FULLPOINTER1 = "0b00000000000000" ;
    defparam fifo_cmd_1_0.FULLPOINTER = "0b11111111111100" ;
    defparam fifo_cmd_1_0.AFPOINTER1 = "0b00000000000000" ;
    defparam fifo_cmd_1_0.AFPOINTER = "0b11111111111100" ;
    defparam fifo_cmd_1_0.AEPOINTER1 = "0b00000000000000" ;
    defparam fifo_cmd_1_0.AEPOINTER = "0b11111111111100" ;
    defparam fifo_cmd_1_0.ASYNC_RESET_RELEASE = "SYNC" ;
    defparam fifo_cmd_1_0.GSR = "DISABLED" ;
    defparam fifo_cmd_1_0.RESETMODE = "ASYNC" ;
    defparam fifo_cmd_1_0.REGMODE = "OUTREG" ;
    defparam fifo_cmd_1_0.CSDECODE_R = "0b11" ;
    defparam fifo_cmd_1_0.CSDECODE_W = "0b11" ;
    defparam fifo_cmd_1_0.DATA_WIDTH_R = 4 ;
    defparam fifo_cmd_1_0.DATA_WIDTH_W = 18 ;
    FIFO8KB fifo_cmd_1_0 (.DI0(Data[4]), .DI1(Data[5]), .DI2(Data[6]), .DI3(Data[7]), 
        .DI4(Data[12]), .DI5(Data[13]), .DI6(Data[14]), .DI7(Data[15]), 
        .DI8(scuba_vlo), .DI9(Data[20]), .DI10(Data[21]), .DI11(Data[22]), 
        .DI12(Data[23]), .DI13(Data[28]), .DI14(Data[29]), .DI15(Data[30]), 
        .DI16(Data[31]), .DI17(scuba_vlo), .CSW0(scuba_vhi), .CSW1(scuba_vhi), 
        .CSR0(RdEn), .CSR1(scuba_vhi), .FULLI(Full_int), .EMPTYI(Empty_int), 
        .WE(WrEn), .RE(scuba_vhi), .ORE(scuba_vhi), .CLKW(WrClock), .CLKR(RdClock), 
        .RST(Reset), .RPRST(RPReset), .DO0(Q[4]), .DO1(Q[5]), .DO2(Q[6]), 
        .DO3(Q[7]), .DO4(), .DO5(), .DO6(), .DO7(), .DO8(), .DO9(), .DO10(), 
        .DO11(), .DO12(), .DO13(), .DO14(), .DO15(), .DO16(), .DO17(), .EF(), 
        .AEF(), .AFF(), .FF());

    assign Empty = Empty_int;
    assign Full = Full_int;


    // exemplar begin
    // exemplar end

endmodule