SCUBA, Version Diamond_3.1_Production (93)
Sun May 18 16:43:06 2014

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2014 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.1_x64\ispfpga\bin\nt64\scuba.exe -w -n fifo_cmd -lang verilog -synth synplify -bus_exp 7 -bb -arch xo2c00 -type ebfifo -depth 256 -width 32 -rwidth 8 -regout -resetmode ASYNC -reset_rel SYNC -no_enable -pe 4 -pf 252 
    Circuit name     : fifo_cmd
    Module type      : ebfifo
    Module Version   : 5.6
    Ports            : 
	Inputs       : Data[31:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
	Outputs      : Q[7:0], Empty, Full, AlmostEmpty, AlmostFull
    I/O buffer       : not inserted
    EDIF output      : fifo_cmd.edn
    Verilog output   : fifo_cmd.v
    Verilog template : fifo_cmd_tmpl.v
    Verilog testbench: tb_fifo_cmd_tmpl.v
    Verilog purpose  : for synthesis and simulation
    Bus notation     : big endian
    Report output    : fifo_cmd.srp
    Element Usage    :
        FIFO8KB : 2
    Estimated Resource Usage:
            EBR : 2