[Device]
Family=machxo2
PartType=LCMXO2-7000HC
PartName=LCMXO2-7000HC-4TG144C
SpeedGrade=4
Package=TQFP144
OperatingCondition=COM
Status=S

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=EFB
CoreRevision=1.1
ModuleName=efb
SourceFormat=Verilog HDL
ParameterFileVersion=1.0
Date=05/13/2014
Time=16:30:00

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
freq=
i2c1=0
i2c1config=0
i2c1_addr=7-Bit Addressing
i2c1_ce=0
i2c1_freq=100
i2c1_sa=10000
i2c1_we=0
i2c2=0
i2c2_addr=7-Bit Addressing
i2c2_ce=0
i2c2_freq=100
i2c2_sa=10000
i2c2_we=0
ufm_addr=7-Bit Addressing
ufm_sa=10000
pll=0
pll_cnt=1
spi=1
spi_clkinv=0
spi_cs=1
spi_en=0
spi_freq=13.33
spi_lsb=0
spi_mode=Both
spi_ib=0
spi_ph=0
spi_hs=0
spi_rxo=0
spi_rxr=0
spi_txo=0
spi_txr=0
spi_we=0
static_tc=Static
tc=0
tc_clkinv=Positive
tc_ctr=1
tc_div=1
tc_ipcap=0
tc_mode=CTCM
tc_ocr=32767
tc_oflow=1
tc_o=TOGGLE
tc_opcomp=0
tc_osc=0
tc_sa_oflow=0
tc_top=65535
ufm=1
wb_clk_freq=40
ufm_usage=SHARED_EBR_TAG
ufm_ebr=2026
ufm_remain=
mem_size=20
ufm_start=
ufm_init=0
memfile=
ufm_dt=hex
wb=1

[Command]
cmd_line= -w -n efb -lang verilog -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 40 -spi -spi_mode Both -spi_freq 13.33 -spi_cs 1 -ufm -ufm_ebr 2026 -mem_size 20 -ufm_0 -wb -dev 7000