module cpld_top
(
	// buffered ISA signals

	input         isa_RESET,    // ISA reset
	inout [15:0]  isa_D,        // ISA data bus (x8)
	input [19:0]  isa_SA,       // ISA system address bus (x20)
	input [23:17] isa_UA,       // ISA address bus (x7)
	input         isa_ALE,      // ISA address latch enable
 	input         isa_SMEMWn,   // ISA system memory write
	input         isa_SMEMRn,   // ISA system memory read
	input         isa_MEMWn,    // ISA memory write
	input         isa_MEMRn,    // ISA memory read
	input         isa_IOWn,     // ISA I/O write
	input         isa_IORn,     // ISA I/O read
	input         isa_SBHEn,    // ISA system byte high enable
	output        isa_READY,    // ISA ready
	output        isa_M16n,     // ISA 16-bit memory supported
	output        isa_IO16n,    // ISA 16-bit I/O supported
	input         isa_AEN,      // ISA DMA address enable
	output        isa_ZWSn,     // ISA Zero wait state enable

	output  [6:0] tp,

	// Misc

	input         sys_CLK_in,   // SYS 20.00 MHz external XO
	input         sys_CFGn,     // Normal (1) vs config (0) DIP SW
	output        sys_LED_R,    // Status LED Red
	output        sys_LED_B     // Status LED Blue
);

	// Clock & reset setup

	wire sys_CLK;
	wire sdr_CLK;
	wire pll_LOCK;

	plla PLLA (
		.CLKI  (sys_CLK_in),  // 20 MHz
		.CLKOP (sdr_CLK),     // 80 MHz
		.CLKOS (sys_CLK),     // 40 MHz
		.LOCK  (pll_LOCK)
	);

	wire sys_RST = isa_RESET;

















	// Select clock to use for ISA bridge logic

	wire isa_CLK = sdr_CLK;







	// ISA strobe aggregation - positive logic

 	wire isa_SMEMW = ~isa_SMEMWn;
	wire isa_SMEMR = ~isa_SMEMRn;
	wire isa_MEMW  = ~isa_MEMWn;
	wire isa_MEMR  = ~isa_MEMRn;
	wire isa_SBHE  = ~isa_SBHEn;

	wire isa_MEM   = isa_SMEMW | isa_MEMW | isa_SMEMR | isa_MEMR;
	wire isa_WE    = isa_SMEMW | isa_MEMW;






	// Synchronize control strobes from ISA bus

	reg isa_IOR;
	reg isa_IOW;

	always @(posedge isa_CLK)
	begin
		isa_IOR <= ~isa_IORn;
		isa_IOW <= ~isa_IOWn;
	end






	// ISA address propagation

	reg [23:17] isa_LA;

	always @(negedge isa_ALE)
		isa_LA <= isa_UA;

	wire [23:0] isa_A = { isa_LA[23:20], isa_SA[19:0] };











	// I/O decode logic

	reg [8:0] io_BASE = 9'b0010_0100_0; // 240 - 247 hex

	wire cs_IO = (isa_A[11:3] == io_BASE) & ~isa_AEN;




	reg [7:0] reg_A;
	reg [7:0] reg_B;
	reg [7:0] reg_C;
	reg [7:0] reg_D;
	reg [7:0] reg_E;
	reg [7:0] reg_F;
	reg [7:0] reg_G;
	reg [7:0] reg_H;





`define state_IDLE            5'b00_000

`define state_XMS_WRITE_SETUP 5'b01_000
`define state_XMS_WRITE       5'b01_001
`define state_XMS_WRITE_WAIT  5'b01_010

`define state_XMS_READ_SETUP  5'b01_100
`define state_XMS_READ        5'b01_101
`define state_XMS_READ_WAIT   5'b01_110

`define state_IO_WRITE        5'b10_000
`define state_IO_WRITE_WAIT   5'b10_001
`define state_IO_READ         5'b10_010
`define state_IO_READ_WAIT    5'b10_011






	reg   [4:0] state = `state_IDLE;
	reg         ready = 1'b1;

	reg [7:0] isa_DAT_U;
	reg [7:0] isa_DAT_L;
	reg       isa_DRV_U = 1'b0;
	reg       isa_DRV_L = 1'b0;









	always @(posedge isa_CLK)
	begin










			case (state)

			`state_IDLE :
			begin

				if (cs_IO & isa_IOR)
				begin
					state <= `state_IO_READ;
					ready <= 1'b0;
				end

				if (cs_IO & isa_IOW)
				begin
					state <= `state_IO_WRITE;
					ready <= 1'b0;
				end

			end














			`state_IO_READ :
			begin

				state <= `state_IO_READ_WAIT;
				ready <= 1'b1;

				isa_DRV_L <= 1'b1;
				isa_DAT_L <= 
					(isa_A[2:0] == 3'b000) ? reg_A :
	                    (isa_A[2:0] == 3'b001) ? reg_B :
	                    (isa_A[2:0] == 3'b010) ? reg_C :
	                    (isa_A[2:0] == 3'b011) ? reg_D :
	                    (isa_A[2:0] == 3'b100) ? reg_E :
	                    (isa_A[2:0] == 3'b101) ? reg_F :
	                    (isa_A[2:0] == 3'b110) ? reg_G : reg_H;
			end

			`state_IO_READ_WAIT :
			begin

				if (~isa_IOR)
				begin
					state <= `state_IDLE;

					isa_DRV_L <= 1'b0;
				end

			end









			`state_IO_WRITE :
			begin

				state <= `state_IO_WRITE_WAIT;
				ready <= 1'b1;

				case (isa_A[2:0])
				3'b000 : reg_A <= isa_D[7:0];
				3'b001 : reg_B <= isa_D[7:0];
				3'b010 : reg_C <= isa_D[7:0];
				3'b011 : reg_D <= isa_D[7:0];
				3'b100 : reg_E <= isa_D[7:0];
				3'b101 : reg_F <= isa_D[7:0];
				3'b110 : reg_G <= isa_D[7:0];
				3'b111 : reg_H <= isa_D[7:0];
				endcase

			end

			`state_IO_WRITE_WAIT :
			begin
				if (~isa_IOW)
					state <= `state_IDLE;
			end









			endcase
		//end
	end










	/*
	 * ISA output logic
	 */

	assign isa_M16n  = 1'bz;
	assign isa_IO16n = 1'bz;

	assign isa_ZWSn = 1'bz;





	assign isa_READY = ready ? 1'bz : 1'b0;

	assign isa_D[15:8] = isa_DRV_U ? isa_DAT_U : 8'hzz;
	assign isa_D[7:0]  = isa_DRV_L ? isa_DAT_L : 8'hzz;











	wire dummy =
		isa_D[0] &
		isa_D[1] &
		isa_D[2] &
		isa_D[3] &
		isa_D[4] &
		isa_D[5] &
		isa_D[6] &
		isa_D[7] &
		isa_D[8] &
		isa_D[9] &
		isa_D[10] &
		isa_D[11] &
		isa_D[12] &
		isa_D[13] &
		isa_D[14] &
		isa_D[15] &
		isa_SA[0] &
		isa_SA[1] &
		isa_SA[2] &
		isa_SA[3] &
		isa_SA[4] &
		isa_SA[5] &
		isa_SA[6] &
		isa_SA[7] &
		isa_SA[8] &
		isa_SA[9] &
		isa_SA[10] &
		isa_SA[11] &
		isa_SA[12] &
		isa_SA[13] &
		isa_SA[14] &
		isa_SA[15] &
		isa_SA[16] &
		isa_SA[17] &
		isa_SA[18] &
		isa_SA[19] &
		isa_UA[17] &
		isa_UA[18] &
		isa_UA[19] &
		isa_UA[20] &
		isa_UA[21] &
		isa_UA[22] &
		isa_UA[23] &
		isa_ALE &
		isa_SMEMWn &
		isa_SMEMRn &
		isa_MEMWn &
		isa_MEMRn &
		isa_IOWn &
		isa_IORn &
		isa_SBHEn &
		isa_AEN &
		isa_RESET &
		sys_CFGn;






	assign tp = {
		isa_DRV_U,
		isa_DRV_L,
		ready | dummy,
		state[4],
		state[3],
		state[2],
		state[1],
		state[0]
	};


	// Temporary

	assign sys_LED_R = reg_A == 8'haa;//state != `state_IDLE;
	assign sys_LED_B = reg_A != 8'haa;//dummy;

endmodule